1. Field of the Invention
The present invention is related generally to communications with host adapter integrated circuits, and in particular to methods of queuing hardware command blocks that are used in communicating tasks to one or more host adapter integrated circuits.
2. Description of Related Art
Hardware control blocks, sometimes called sequencer control blocks or SCSI control blocks (SCBs), are typically used for transferring information between a software host adapter device driver in a host computer and a host adapter integrated circuit that controls operations of one or more peripheral devices. Methods for queuing SCBs are known to those of skill in the art. For example, see copending and commonly assigned U.S. patent application Ser. No. 07/964,532 (now U.S. Pat. No. 5,659,690) entitled "Intelligent SCSI Bus Host Adapter Integrated Circuit," of Craig A. Stuber et al. filed on Oct. 16, 1992, which is incorporated wherein by reference in its entirety. See also copending and commonly assigned U.S. patent application Ser. No. 08/269,491 (now U.S. Pat. No. 5,625,800) entitled "A Sequencer Control Block Array External To A Host Adapter Integrated Circuit" of B. Arlen Young, et al. filed on Jun. 30, 1994; and also U.S. Pat. No. 5,564,023 entitled "Method for Accessing A Sequencer Control Block By A Host Adapter Integrated Circuit" of B. Arlen Young issued on Oct. 8, 1996, each of which is incorporated herein by reference in its entirety.
Typically, the software host adapter device driver, that transmits SCBs to the host adapter integrated circuit, included an operating system specific module (OSM) and a hardware interface module (HIM) that both were maintained in the host computer system. The OSM knew nothing about the hardware in the host adapter integrated circuit and communicated with both the host computer operating system and the HIM. The HIM communicated only with the host adapter integrated circuit and the OSM. The OSM supplied information to the HIM that in turn built a SCB. Alternative methods for queuing the SCBs by the HIM and the host adapter integrated circuit are described in the patents referenced above and so are not repeated herein.
In another application illustrated in FIG. 1, only a single host adapter device 120 is illustrated. However, multiple host adapter devices 120 could be used. Host adapter device 120 has an internal microprocessor 125, referred to as sequencer 125. Sequencer 125 controls a DMA engine 140 and is coupled to random access memory 150, and two counters 131 and 132. DMA engine 140 is coupled to host computer I/O bus 160, such as a PCI bus. Further, as is known to those of skill in the art, host adapter device 120 includes bus interface circuits and other circuits that are not shown because the additional circuits are not of importance to understanding the prior art queuing of hardware command blocks.
In this example, an external microprocessor is host computer microprocessor 105. Similar to the operations described above, in response a call from a process executing on microprocessor 105, an OSM 101 executing on microprocessor 105 sends information to HIM 102, that also executes on microprocessor 105. HIM 102 uses the information to build a transfer command block (TCB), that is similar to a sequencer command block.
HIM 102 manages host adapter device 120. Task requests from HIM 102 to host adapter device 120 are made via TCBs. HIM 102 delivers new TCBs to sequencer 125 for execution, and receives completed TCBs from sequencer 125 via queues common to both HIM 102 and sequencer 125.
HIM 102 delivers new TCBs via a new TCB pointer queue 112, and receives completed TCBs via a done TCB pointer queue (not shown). These queues are circular, contiguous lists of pointers to TCBs, or alternatively TCBs, with head and tail pointers delimiting each queue. Each queue of TCB pointers defines a queue of TCBS. The queues are not linked lists, because a queue element does not contain information that relates that queue element to another element of the queue.
Only new TCB pointer queue 112 in host memory 111 is considered herein. A head pointer 156 to the head TCB pointer in new TCB pointer queue 112 is managed by sequencer 125, and a tail pointer 116 to the tail TCB pointer in new TCB pointer queue 112 is managed by HIM 102. As explained more completely below, counters 131 and 132 in host adapter device 120 enable HIM 102 to communicate to sequencer 125 how many TCBs are available via new TCB pointer queue 112. Specifically, HA queued TCB counter 131 is written only by HIM 102, and is only read by sequencer 125. Removed TCB counter 132 is accessed only by sequencer 125.
When HIM 102 builds a new TCB, HIM 102 allocates a site in HA TCB array 155 for the new TCB. The new TCB pointer includes the site in HA TCB array 155, and the host memory address of the storage location of the TCB in host TCB array 115.
HIM 102 maintains tail pointer 116 to identify the next free location in TCB pointer queue 112. HIM 102 appends the new TCB pointer at the next host memory address in queue 112 that immediately follows the address stored in tail pointer 116.
After appending the TCB pointer to TCB pointer queue 112, HIM advances tail pointer 116 to the address of the new end of queue 112. When the tail address advances beyond the address allocation for TCB pointer queue 112, HIM 202 replaces the out-of-bounds tail address with the base address of TCB pointer queue 112, according to the definition of a circular queue.
For each TCB pointer appended to TCB pointer queue 112, HIM 102 increments the count in queued TCB counter 131 on host adapter device 120. HIM 102 also maintains a copy of the value of queued TCB counter 131 in queued TCB counter 117 in host memory 111. Thus, HIM 102 does not have to read counter 131 prior to the increment which saves a PIO on host computer bus 160.
Queued TCB counters 117 and 131 maintain a running count of the total number of TCB pointers appended to TCB pointer queue 112 since initialization. Counters 117 and 131 roll over to zero when tail pointer 116 rolls over to the base address of TCB pointer queue 112.
Sequencer 125 uses removed TCB counter 132 to keep a running count of the TCB pointers removed from TCB pointer queue 112 since initialization. Thus, to determine whether an additional TCB or TCBs are available for processing, sequencer 125 compares the values of removed TCB counter 132 and queued TCB counter 131.
Sequencer 125 determined that there was at least one new TCB pointer in TCB pointer queue 112 when the value of removed TCB counter 132 was not equal to the value of queued TCB counter 131. Sequencer 125 uses head pointer 156 to determine the location of the next TCB pointer to transfer. Recall that the TCB pointers are stored in contiguous memory locations. Head pointer 156 is the address of the next TCB pointer to be removed from queue 112. Since TCB pointers are to be removed from TCB pointer queue 112 in order only, and a TCB pointer is never skipped, sequencer 125 knows that the next TCB pointer is at the address in queue 112 that is in head pointer 156.
Sequencer 125 configures DMA engine to transfer the new TCB pointer at the head of TCB pointer queue 112 to a temporary buffer. The new TCB pointer specifies a site in HA TCB array 155 and the address in host memory 111 where the TCB is stored. This information is provided to DMA engine 140 that in turn loads the TCB in the specified TCB site in HA TCB array 155 for subsequent execution. Each TCB site in HA TCB array 155 is 128 bytes in size. Practical arrays can contain in excess of 1500 sites.
Following the two DMA transfers, sequencer 125 increments removed TCB counter 132 and advances head pointer 156 in preparation for accessing another TCB pointer in queue 112 at a later time. Head pointer rollover is handled in the same manner as described for tail pointer rollover. Removed TCB counter 132 rolls over to zero when head pointer 156 rolls over to the base address of queue 112.
This example used a circular queue of TCB pointers, which minimized the number of contiguous memory locations required. However, some applications require a circular queue of TCBs. The use of a circular queue of TCBs eliminates the DMA transfer of the TCB pointers, but such a circular queue requires a large number of contiguous memory locations in a block of memory 111. With the exception of the elimination of the TCB pointer DMA transfer, the operation of the circular queue of new TCBs is the same as the operation described above.
Also, HIM 102 must maintain a copy of a TCB until after execution of the TCB has been completed by host adapter 120. Execution of some TCBs can take a very long time, during which the TCB site in a circular queue will need to be reused for delivering a different TCB. Therefore, HIM 102 must create two copies of a TCB: one in the circular queue, and the other for future reference. This further complicates the management and use of memory 111. A method is needed for queuing new TCBs that does not suffer from the shortcomings associated with a circular queue of TCBs or of TCB pointers.